The present invention relates to a method to reduce charge interface trap density and channel hot carrier degradation in silicon metal oxide semiconductor transistors (MOSFET). The method uses deuterium enhanced oxidation to reduce the density of silicon dangling bonds at the silicon-silicon oxide interface.
Integrated circuits are comprised of semiconductor devices which are fabricated on silicon wafers and/or substrates. The main building block of CMOS integrated circuits is the enhancement mode MOSFET. The enhancement mode MOSFET (or MOSFET) is a four terminal device comprising a source, a drain, a substrate, and a gate terminal. In general, voltage applied to the gate controls the flow of electrons or holes from the source terminal to the drain terminal. The gate of the MOSFET comprises a gate dielectric layer over the silicon surface and a conductive layer over the gate dielectric. The MOSFET shown in FIG. 1 is an NMOS device. Here the substrate 10 is p-type silicon and the source region 20 and drain region 30 are doped n-type. The gate dielectric 40 and the conductive gate terminal 50 are also shown. In operation, a positive voltage is applied to the gate 50 and drain 30 with the source 20 and substrate 10 grounded. Under certain voltage conditions a depletion layer 60 and an inversion layer or channel 70 will form beneath the gate and the transistor will be xe2x80x9conxe2x80x9d. The flow of current in the transistor is due to the flow of carriers in the inversion layer and it is this flow of inversion charge that determines the transistor properties. For a NMOS transistor the inversion layer will comprise electrons. As illustrated in FIG. 1, the inversion layer 70 is confined to the interface between the silicon substrate 10 and the gate dielectric 40. The physical and electrical characteristics of the silicon substrate 10 and gate dielectric 40 interface is therefore crucial in determining transistor performance.
Shown in FIG. 2 are the main sources of charge in a silicon oxide gate dielectric layer that affect the inversion layer and thus transistor performance. The fixed oxide charge 80 and the mobile ionic charge 90 are due to intrinsic and extrinsic defects in the oxide. These defects are usually distributed throughout the oxide and will have a second order effect on the inversion layer 70. The defects that will have the largest effect on the inversion layer 70 and thus transistor performance will be the interface states 100. These interface states 100 exist in all silicon oxide-silicon interfaces and are due to the presence of silicon dangling bonds. These silicon dangling bonds are unsaturated bonds and can be due to a number of different factors including chemical and lattice mismatch, metallic impurities, and radiation. The energy states associated with these dangling bonds can interact with the silicon and thus the inversion layer 70. A good control of these interface states is thus very important because of the large deleterious effect these states have on transistor performance. Under normal use hot carriers are produced in the inversion layer region of the transistor. These hot carriers can enter the dielectric gate layer and become trapped in the interface states where they cause a shift in the threshold voltage and transconductance of the transistor. Such shifts often lead to a degradation in transistor and integrated circuit performance. Interface states also have a strong effect on carrier surface mobility and their density is related to the 1/f noise in MOSFETs. In addition to affecting transistor performance interface states can also cause charge transfer losses in charge coupled devices, as well as affecting the refresh time in DRAMs. Currently, silicon wafers are sintered at 450-500xc2x0 C. in hydrogen, wet nitrogen or forming gas to reduce the density of the interface states. This low temperature anneal is usually combined with the sintering step after metallization and can reduce the concentration of these interface states to mid 1010 cmxe2x88x922 eVxe2x88x921 for silicon (100) material. Reducing this concentration further will result in improvements in transistor performance. Such improvements are becoming increasingly necessary as transistors are scaled in the ultra large scale integration era. There is therefore a need for a method for reducing the concentration of interface states below that currently obtainable.
The method of the instant invention comprises a deuterium based steam oxidation process to form an oxide dielectric film on a silicon substrate. The method comprises: flowing a first amount of oxygen; flowing a second amount of deuterium to form a oxidizing vapor with said first amount of oxygen; inserting a silicon substrate with an upper surface in said oxidizing vapor; and increasing the temperature of said silicon substrate in said oxidizing vapor to form a dielectric layer on said upper surface. Other technical advantages will be readily apparent to one skilled in the art from the following FIGUREs, description, and claims.